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SN74HCS72 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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SN74HCS72 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 19 page ![]() VOH VOL Output VCC 0 V Input tf tr 90% 10% 90% 10% tr 90% 10% tf 90% 10% 50% Input 50% VCC 0 V 50% 50% VOH VOL tPLH (1) tPHL (1) VOH VOL tPHL (1) tPLH (1) Output Output 50% 50% Clock Input 50% VCC 0 V 50% 50% VCC 0 V tsu Data Input th CL (1) RL From Output Under Test VCC Test Point S1 S2 50% tw Input 50% VCC 0 V 8 SN74HCS72 SCLS801 – FEBRUARY 2020 www.ti.com Product Folder Links: SN74HCS72 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 7 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. CL includes probe and test-fixture capacitance. Figure 5. Load Circuit Figure 6. Voltage Waveforms, Pulse Duration Figure 7. Voltage Waveforms, Setup and Hold Times Voltage Waveforms, Propagation Delay specifications tPLH and tPHL are the same as tpd. Figure 8. Voltage Waveforms Propagation Delays Figure 9. Voltage Waveforms, Input and Output Transition Times |
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