TFP503

PanelBus HDCP DIGITAL RECEIVER

SLDS149 − AUGUST 2004

15

POST OFFICE BOX 655303

TFP503 modes of operation

The TFP503 provides system design flexibility and value by providing the system designer with configurable

options or modes of operation to support varying system architectures. The following table outlines the various

panel modes that can be supported along with appropriate external control pin settings.

PANEL

PIXEL RATE

ODCK LATCH EDGE

ODCK

DFO

PIXS

OCK_INV

TFT or 16-bit DSTN

1 pixel/clock

Falling

Free run

0

0

0

TFT or 16-bit DSTN

1 pixel/clock

Rising

Free run

0

0

1

TFT

2 pixel/clock

Falling

Free run

0

1

0

TFT

2 pixel/clock

Rising

Free run

0

1

1

24-bit DSTN

1 pixel/clock

Falling

Gated low

1

0

0

None

1 pixel/clock

Rising

Gated low

1

0

1

24-bit DSTN

2 pixel/clock

Falling

Gated low

1

1

0

24-bit DSTN

2 pixel/clock

Rising

Gated low

1

1

1

TFP503 output driver configurations

The TFP503 provides flexibility by offering various output driver features that can be used to optimize power

consumption, ground bounce, and power-supply noise. The following sections outline the output driver features

and their effects.

Output driver power down (PDO = low.) Pulling PDO low places all the output drivers, except CTL1 and SCDT,

into a high-impedance state. A weak pulldown (approximately 10

µA) gradually pulls these high-impedance

outputs to a low level to prevent the outputs from floating. The SCDT output, which indicates a link-disabled or

link-inactive state, can be tied directly to the PDO input to disable the output drivers when the link is inactive

or when the cable is disconnected. An internal pullup resistor on the PDO terminal defaults the TFP503 to the

normal nonpower-down output drive mode if left unconnected.

Drive strength (ST = high for high drive strength, ST = low for low drive strength.) The TFP503 allows for

selectable output drive strength on the data, control, and ODCK outputs. See the dc specifications table for the

two times the drive as the low output drive strength does.

Time-staggered pixel output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high.)

Setting STAG = low will time-stagger the even and odd pixel outputs so as to reduce the amount of instantaneous

current surge from the power supply. Depending on the PCB layout and design, this can help reduce the amount

of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even

Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the TFP503

drive strength and staggered pixel options allow flexibility to reduce system power supply noise, ground bounce,

and EMI.

Power management. The TFP503 offers several system power-management features. The output driver

power-down (PDO = low) mode is an intermediate mode which offers several uses. During this mode, all output

drivers except SCDT and CTL1 are driven to a high-impedance state while the rest of the device circuitry

remains active.

The TFP503 power down (PD = low) is a complete power down in that it powers down the digital core, the analog

circuitry, and output drivers. All output drivers are placed into a high-impedance state. All inputs are disabled

except for the PD input. The TFP503 does not respond to any digital or analog inputs until PD is pulled high.