TFP503

PanelBus HDCP DIGITAL RECEIVER

SLDS149 − AUGUST 2004

13

POST OFFICE BOX 655303

high-bandwidth digital content protection (HDCP) overview (continued)

The downstream encryption described in the specification High-bandwidth Digital Content Protection System

Specification (Revision 1.0) protects video data passing from the HDCP transmitter to the HDCP receiver via

a DVI link. The HDCP transmitter encrypts video data and the receiver decrypts the data as shown in Figure 13.

The HDCP keys must also be protected from access. An encryption scheme protects the HDCP device key

HDCP device keys are needed, the encrypted values are read from the EEPROM, decrypted, and then enable

interface is encrypted. TI’s HDCP solution provides real advantages with respect to lower systems-level cost,

ease of implementation, high performance, and exceptional security.

S/W

Application

Program

CPU

and

North

Bridge

and

Graphics

Controller

TFP510 or TFP513

DVI-HDCP TX

(PC’s DVI Output)

PROM

Key

Decrypt

I2C Slave

Interface

DE

Pixel Data

Clock

Input

Stream

Encrypted Keys

A Keys and KSV

I2C

I2C

TFP503

DVI-HDCP RX

(Display’s DVI Input)

PROM

Key

Decrypt

I2C Slave

Interface

Channel 2

Channel 0

Channel C

HDCP Encrypted

TMDS Link

Encrypted Keys

B Keys and KSV

I2C

I2C

Channel 1

EDID

PROM

Control and Authentication and Key Exchange

KSV = Key Selection Vector

DE

Pixel Data

Clock

Output

Stream

Figure 13. TI’s HDCP Implementation for PC and Display System

TFP503 clocking and data synchronization

The TFP503 receives a clock reference from the DVI transmitter, such as the TFP510 or TFP513, that has a

T.M.D.S. encoded data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10

times the pixel rate. For example, the required pixel rate to support an UXGA resolution with 60-Hz refresh rate

is 165 MHz. The T.M.D.S. serial bit rate is 10x the pixel rate or 1.65 Gb/s. Due to the transmission of this

high-speed digital bit stream on three separate channels (or twisted-pair wires) of long distances (3 to 5 meters),

phase synchronization between the data steams and the input reference clock is not assured. In addition, skew

between the three data channels is common. The TFP503 uses a 4x oversampling scheme of the input data

Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of

high-speed serial data transmission. The TFP503 is designed for high jitter tolerance.