AX58100LT datasheet(56/71 Pages) ASIX

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AX58100

EtherCAT Slave Controller

Figure 4-25: PDI Local Bus Sequence of two write accesses and a read access

Note: The first write access to ADR1 is performed after the first rising edge of WR. After that, the ESC is internally busy writing

to ADR1. After CS is deasserted, BUSY is not driven any more, nevertheless, the ESC is still writing to ADR1.

Hence, the second write access to ADR2 is delayed because the write access to ADR1 has to be completed first. So, the second

rising edge of WR must not occur before BUSY is gone. After the second rising edge of WR, the ESC is busy writing to ADR2.

This is reflected with the BUSY signal as long as CS is asserted.

The third access in this example is a read access. The ESC is still busy writing to ADR2 while the falling edge of RD occurs. In

this case, the write access to ADR2 is finished first, and afterwards, the read access to ADR3 is performed. The ESC signals

BUSY during both write and read access

Figure 4-26: PDI Local Bus Write access (write after falling edge LWRn)

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