MPC92433 datasheet(13/20 Pages) FREESCALE

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Advanced Clock Drivers Devices

Freescale Semiconductor

MPC92433

LOCK Detect

The LOCK detect circuitry indicates the frequency-lock

status of the PLL by setting and resetting the pin LOCK and

frequency lock state, the assertion of the LOCK signal is

delayed at least 256 reference clock cycles to prevent

signaling temporary PLL locks during frequency transitions.

The LOCK signal is deasserted when the PLL lost lock, for

instance when the reference clock is removed: the LOCK

signal goes low after missing at least two fref clock cycles

(NREF(UNLOCK)). The PLL may also lose lock when the PLL

feedback-divider M or pre-divider P is changed or the

DEC/INC command is issued. The PLL may not lose lock as

a result of slow reference frequency changes. In any case of

losing LOCK, the PLL attempts to re-lock to the reference

frequency.

Output Clock Stop

Asserting CLK_STOPx will stop the respective output

clock in logic low state. The CLK_STOPx control is internally

synchronized to the output clock signal, therefore, enabling

and disabling outputs does not produce runt pulses. See

Figure 5.The clock stop controls of the QA and QB outputs

are independent on each other. If the QB runs at half of the

QA output frequency and both outputs are enabled at the

same time, the first clock pulse of QA may not appear at the

same time of the first QB output. (See Figure 6.) Concident

rising edges of QA and QB stay synchronous after the

assertion and de-assertion of the CLK_STOPx controls.

Asserting MR always resets the output divider to a logic low

output state, with the risk of producing an output runt pulse.

Figure 5. Clock Stop Timing for NB = 0 (fQA = fQB)

Figure 6. Clock Stop Timing for NB = 1 (fQA = 2 fQB)

CLK_STOPx

(Disable)

(Enable)

tP_DIS

tP_EN

CLK_STOPA,B

(Disable)

(Enable)

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