MPC92433 datasheet(9/20 Pages) FREESCALE

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Advanced Clock Drivers Devices

Freescale Semiconductor

MPC92433

PLL Divider Configuration

Programming the MPC92433

The MPC92433 has a parallel and a serial configuration

interface. The purpose of the parallel interface is to directly

configure the PLL dividers through hardware pins without the

overhead of a serial protocol. At device startup, the device

always obtains an initial PLL frequency configuration through

the parallel interface. The parallel interface does not support

reading the PLL configuration.

The serial interface is I2C compatible. It allows reading and

writing devices settings by accessing internal device

registers. The serial interface is designed for host-controller

access to the synthesizer frequency settings for instance in

frequency-margining applications.

Using the Parallel Interface

The parallel interface supports write-access to the PLL

frequency setting directly through 15 configuration pins (P,

M[9:0], NA[2:0], and NB). The parallel interface must be

enabled by setting PLOAD to logic low level. During

PLOAD = 0, any change of the logical state of the P, M[9:0],

NA[2:0], and NB pins will immediately affect the internal PLL

divider settings, resulting in a change of the internal VCO-

frequency and the output frequency. The parallel interface

mode disables the I2C write-access to the internal registers;

however, I2C read-access to the internal configuration

registers is enabled.

Upon startup, when the device reset signal is released

(rising edge of the MR signal), the device reads its startup

configuration through the parallel interface and independent

on the state of PLOAD. It is recommended to provide a valid

PLL configuration for startup. If the parallel interface pins are

left open, a default PLL configuration will be loaded. After the

low-to-high transition of PLOAD, the configuration pins have

no more effect and the configuration registers are made

accessible through the serial interface.

Using the I2C Interface

PLOAD = 1 enables the programming and monitoring of

the internal registers through the I2C interface. Device

interface using SDA (configuration data) and SCL

(configuration clock) signals. The MPC92433 acts as a slave

device at the I2C bus. For further information on I2C it is

recommended to refer to the I2C bus specification (version

2.1).

PLOAD = 0 disables the I2C-write-access to the configura-

tion registers and any data written into the register is ignored.

However, the MPC92433 is still visible at the I2C interface

and I2C transfers are acknowledged by the device. Read-ac-

cess to the internal registers during PLOAD = 0 (parallel pro-

gramming mode) is supported.

Note that the device automatically obtains a configuration

using the parallel interface upon the release of the device

reset (rising edge of MR) and independent on the state of

PLOAD. Changing the state of the PLOAD input is not

supported when the device performs any transactions on the

I2C interface.

Programming Model and Register Set

The synthesizer contains two fully accessible configuration

registers (PLL_L and PLL_H) and a write-only command

through the I2C interface requires two steps: 1) writing a valid

PLL configuration to the configuration registers and 2)

loading the registers into the PLL by an I2C command. The

PLL frequency is affected as a result of the second step.

This two-step procedure can be performed by a single I2C

transaction or by multiple, independent I2C transactions. An

alternative way to achieve small PLL frequency changes is to

use the increment or decrement commands of the

Table 8. Pre-PLL Divider P

PValue

0fREF ÷ 2

1fREF ÷ 4

Table 9. Post-PLL Divider NA and NB

NA2

NA1

NA0

fOUT (QA)

fOUT (QB)

fVCO ÷ 2

fVCO ÷ 32

fVCO ÷ 8

fVCO ÷ 12

fVCO ÷ 4

fVCO ÷ 6

fVCO ÷ 16

0n/a

n/a

fVCO ÷ 2

fVCO ÷ 4

1n/a

n/a

fVCO ÷ 8

fVCO ÷ 16

1n/a

n/a

fVCO ÷ 4

fVCO ÷ 8

fVCO ÷ 6

fVCO ÷ 12

fVCO ÷ 16

fVCO ÷ 32

1n/a

n/a

Table 10. Feedback Divider Configuration

Feedback

Divider M

M9 M8 M7 M6 M5 M4 M3 M2 M1 M0

Default

Table 11. PLL Pre/Post Divider Configuration (N, P)

Post-D.

210

Post-D.

Pre-D.

NA2

NA1

NA0

Default

010

Default

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