CS6403 datasheet(19/54 Pages) CIRRUS

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B11

B10

RST

SLP

AGCRD

NECD

FHPD

NHPD

PED

GBC1

GBC0

AECB1 AECB0

This register is read from the SSI by the CPU only upon exit from Reset and Sleep. This register is

cleared at reset except for B3-B0 (see below).

BIT

NAME

VALUE

FUNCTION

RST

Reset

Normal operation.

Control registers and RAMs are cleared, and then

control constants are loaded into Data RAM. SSI is

still operational, though writes to any control bit

except RST are ignored.

SLP

Sleep

Normal operation.

The CPU and AFP on the CS6403 are powered

down. Control registers and RAMs are unaffected.

Serial Data transactions that occur during power

down are transferred directly between the SSI and

the codec, bypassing the CPU. As a result, echo is

passed uncancelled.

AGCRD

AGC-Rescale Disable

SPKROUT volume is scaled to full-scale after

peak-limiter.

SPKROUT signal is peak-limited version of far-end

input.

NECD

NEC Disable

10 ms of the available 64 ms of EC taps are

allocated by default to network echo cancellation.

No taps are allocated to network echo cancellation.

FHPD

FE_IN High-Pass

Disable

A high-pass filter ((1-D)/(1-0.75D)) is inserted in the

far-end input signal path.

This filter is bypassed.

NHPD

NE_IN High-Pass Disable

A high-pass filter ((1-D)/(1-0.75D)) is inserted in the

near-end input signal path.

This filter is bypassed.

Companding Enable

Data in 16-bit data modes is linear (i.e., not

companded).

b15 is still used as the steering bit, but if b15=0, the

least significant 8 bits are companded data.

PED

Pre-Emphasis Disable

A pre-emphasis filter is placed before the input to the

adaptive filter.

This filter is bypassed.

"R" indicates value after Reset

CS6403

DS192PP6

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