CS5368 datasheet(24/39 Pages) CIRRUS

24 / 39 page

DS624A1

CS5368

4.6.6

Using DIF1 and DIF0 to Set Serial Audio Interface Format

The format of the data at the Serial Audio Interface ports is controlled by the settings of the DIF1 and DIF0

pins in standalone mode, or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in Control-

Port Mode.

Table 3. DIF1 and DIF0 Pin Settings

4.6.7

Master Mode Audio Clocking

Figure 11. "Master Mode Clock Dividers" shows the configuration of the MCLK dividers and the sample

rate dividers while in Master Mode.

Figure 11. Master Mode Clock Dividers

4.6.8

Slave Mode Audio Clocking

In Slave Mode, the sampling rate is auto-set by examining the incoming MCLK and LRCK/FS signals.

LRCK/FS and SCLK operate as inputs in Slave Mode. It is recommended that the LRCK/FS be synchro-

nously derived from the Master clock, and it must be equal to the desired sampling rate, Fs.

DIF1

DIF0

Mode

Left Justified

I²S

TDM (2 wire)

TDM (4 wire)

÷ 1 2 8

÷ 6 4

LR C K /

F S

S ingle

Sp e e d

Qu a d

Sp e e d

D ouble

Sp e e d

÷ 2

÷ 4

÷ 1

SC L K

Sin g le

S peed

Q uad

S peed

D ouble

S peed

÷ 2 5 6

CM O D E

MD I V

n/ a

MC L K

÷ 1

÷ 1. 5

÷ 2

÷ 1

÷ 2

÷ 1

bit

CM O D E

MD IV 1

MD IV 0

0/ 1

0 / 1

M C L K

DIV ID E RS

S A M P L E

RA T E

DIV ID E RS

CS5368 bảng dữ liệu(PDF) 24 Page - Cirrus Logic

CS5368 bảng dữ liệu(HTML) 24 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

bảng dữ liệu tải về

Link URL