CS5368 datasheet(16/39 Pages) CIRRUS

16 / 39 page

DS624A1

CS5368

SERIAL AUDIO INTERFACE - TDM TIMING

The serial audio port is a 3 pin interface consisting of SCLK, LRCK and SDOUT.

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.

Notes:

TDM Quad-Speed Mode only specified to operate correctly at VLS

≥ 3.14 V.

In Master mode, the SCLK/LRCK ratio is fixed at 256. In Slave Mode, the SCLK/RCLK ratio can be set

according to preference. However, chip performance is guaranteed only when using the ratios in Section

4.6.9

Master and Slave Clock Frequencies on page 29.

Figure 3. TDM Timing

OVERFLOW TIMEOUT

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 15 pF, timing threshold is 50% of VLS.

Table 1. Overflow Timeout

Parameter

Symbol

Min

Typ

Max

Unit

Sample Rates

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode1

108

216

kHz

SCLK Frequency2

SCLK Period

1/(256*54 kHz)

SCLK Duty Cycle

tPERIOD

tHIGH1

72.3

256*Fs

FS setup

before SCLK rising

FS hold

after SCLK rising

FS width

in SCLK cycles

tSETUP1

tHOLD1

tHIGH2

250

SDOUT setup

before SCLK rising

SDOUT hold

after SCLK rising

tSETUP2

tHOLD2

Parameter

Symbol

Min

Typ

Max

Unit

OVFL time-out on overrange condition

Fs = 44.1 kHz

Fs = 192 kHz

(217-1)/Fs

2972

683

SDOUT

SCLK

data

HOLD2

SET UP2

HOLD1

SET UP1

newframe

data

PERIOD

HIGH1

HIGH2

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