CS4922

12

Notes: 15. The table above assumes data is output on the falling edge and latched on the rising edge. The SCLK

edge is selectable in setting the EDG bit in the ASICN register. The diagram is for EDG = 1.

Parameter

Symbol

Min

Typ

Max

Units

SCLK Frequency

-

-

12.5

MHz

SCLK Pulse Width Low

25

-

-

ns

SCLK Pulse Width High

25

-

-

ns

SCLK rising to FSYNC edge delay

(Note 15)

20

-

-

ns

SCLK rising to FSYNC edge setup

(Note 15)

20

-

-

ns

SDATA valid to SCLK rising setup

(Note 15)

20

-

-

ns

SCLK rising to SDATA hold time

(Note 15)

20

-

-

ns

Rise time of SCLK

--

20

ns

sckh

t

sfs

t

sfds

t

sss

t

ssh

t

sckl

t

SDATA

SCLK

FSYNC

sclr

t

Figure 4. Serial Audio Port Timing