CS4922

10

11. Data must be held for sufficient time to bridge the 300ns transition time of SCK/SCL.

communications for more information.

13. REQ will only go HIGH if there is no data in the SCPOUT register at the rising edge of SCL/SCK during

a READ operation as shown. DSP frequency is 20 MHz. Pull-up resistor is 2 k

Ω C

14. if REQ went HIGH as indicated in Note 13 then REQ will hold HIGH at least until the next rising edge of

SCK/SCL. If data is in the SCPOUT register at this time REQ will go active LOW again. This condition

should be treated as a new READ process. The address and R/W should be sent again following a new

START condition.

Parameter

Symbol

Min

Max

Units

(Note 10)

SCK/SCL Clock Frequency

(slow mode)

(fast mode)

100

400

kHz

Bus Free Time Between Transmissions

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

4.0

µs

Clock Low Time

slow

fast

4.7

1.2

µs

Clock High Time

slow

fast

4.0

1.0

µs

SDA Setup Time to SCK/SCL Rising

250

ns

SDA Hold Time from SCK/SCL Falling

(Note 11)

0

µs

Rise Time of Both SDA and SCK/SCL

(Note 12)

50

ns

Fall Time of Both SDA and SCK/SCL

300

ns

Time from SCK/SCL Falling to CS4920 ACK

40

ns

Time from SCK/SCL Falling to SDA

Valid During READ Operation

40

ns

Time from SCK/SCL Rising to REQ Rising

(Note 13)

200

ns

Hold Time for REQ from SCK/SCL Rising

(Note 14)

0ns

Rise Time for REQ

(Note 13)

50

ns

Fall Time for REQ

(Note 14)

20

ns

Setup Time for Stop Condition

4.7

µs