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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TUSB216 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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TUSB216 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 33 page  tBUF tHDSTA tR tLOW tHDDAT t HIGH tF tSUDAT tSUSTA tHDSTA tSUSTO P S S P SDA SCL 30% 70% 30% 70% tSTABLE VCC RSTN tRSTN_PW VIL(MAX) VCC(MIN) tRAMP 8 TUSB216 SLLSEZ6A – FEBRUARY 2019 – REVISED DECEMBER 2019 www.ti.com Product Folder Links: TUSB216 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 6.7 Timing Requirements MIN NOM MAX UNIT POWER UP TIMING TRSTN_PW Minimum width to detect a valid RSTN signal assert when the pin is actively driven low 100 µs TSTABLE VCC must be stable before RSTN de-assertion 300 µs TREADY Maximum time needed for the device to be ready after RSTN is de- asserted. 500 µs TRAMP VCC ramp time 100 ms TRAMP VCC ramp time 0.2 ms I2C (STD) tSUSTO Stop setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 4 µs tHDSTA Start hold time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 4 µs tSUSTA Start setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 4.7 µs tSUDAT Data input or False start/stop, setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 250 ns tHDDAT Data input or False start/stop, hold time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz STD 5 µs tBUF Bus free time between START and STOP conditions 4.7 µs tLOW Low period of the I2C clock 4.7 µs tHIGH High period of the I2C clock 4 µs tF Fall time of both SDA and SCL signals 300 ns tR Rise time of both SDA and SCL signals 1000 ns Figure 1. Power On and Reset Timing Figure 2. I2C Timing |
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