LPC47M14X datasheet(101/205 Pages) SMSC

101 / 205 page

SMSC DS – LPC47M14X

Page 101

Rev. 03/19/2001

6.12 INTERRUPT GENERATING REGISTERS

The LPC47M14x contains on-chip Interrupt Generating Registers to enable external software to generate IRQ1

through IRQ15 on the Serial IRQ Interface. These registers, INT_GEN1 and INT_GEN2 as shown below, are located

in the Logical Device A Runtime Block, at offsets 54h and 55h, respectively, from the Runtime Block base address

setting (set at Index 0x60 and 0x61, Logical Device A Configuration Registers).

Registers INT_GEN1 and INT_GEN2 are enabled to output to the Serial IRQ stream by setting Logical Device A

Configuration Register, at Index 0xF1, Bit [0] to ‘1’. When Bit [0] is set to ‘0’, INT_GEN1 and INT_GEN2 are

prevented from outputting to the Serial IRQ stream.

Writing Bits 0 through 8 to ‘0’ in registers INT_GEN1 and INT_GEN2 enable the corresponding interrupt (INT1

through INT15) to be asserted (made active) in the Serial IRQ stream. Producing an interrupt in the Serial IRQ stream

by writing these bits to ‘0’ overrides other interrupt sources for the Serial IRQ stream. No other functional logic in the

LPC47M14x sets bits in these registers. The asserted interrupt in the Serial IRQ stream from registers INT_GEN1

and INT_GEN2 is removed by writing the corresponding bit to ‘1’.

INT_GEN1 Register

NAME

INT_GEN1

LOCATION

Runtime Block Offset 54h

DEFAULT VALUE

0xFF

ATTRIBUTE

Read/Write

SIZE

8 bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

nINT 7

nINT 6

nINT 5

nINT 4

nINT 3

nINT2

nINT1

Reserved

INT_GEN2 Register

NAME

INT_GEN2

LOCATION

Runtime Block Offset 55h

DEFAULT VALUE

0xFF

ATTRIBUTE

Read/Write

SIZE

8 bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

nINT 15

nINT 14

nINT 13

nINT 12

nINT 11

nINT 10

nINT 9

nINT 8

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