DSC6162JE2B-B datasheet(4/24 Pages) MICROCHIP

4 / 24 page

DSC61XXB

DS20006155A-page 4

 2019 Microchip Technology Inc.

Output Logic Levels

VOH

0.8 x VDD

——

Output Logic High, I = 3 mA,

Std. Drive

Output Logic High, I = 6 mA,

High Drive

VOL

—

0.2 x VDD

Output Logic Low, I = –3 mA,

Std. Drive

Output Logic Low, I = –6 mA,

High Drive

Output Transition Time

Rise Time/Fall Time

tRX/tFX

—1

1.5

DSC61x2

High Drive,

20% to 80%

CL = 15 pF

VDD = 1.8V

—0.5

1.0

VDD = 2.5V/3.3V

tRY/tFY

—1.2

2.0

DSC61x1

Std Drive,

20% to 80%

CL = 10 pF

VDD = 1.8V

—0.6

1.2

VDD = 2.5V/3.3V

Period Jitter, RMS

JPER

—8.5

—

psRMS

fOUT =

27 MHz

VDD = 1.8V

—7

—

VDD = 2.5V/3.3V

Cycle-to-Cycle Jitter

(Peak)

JCy–Cy

—50

fOUT =

27 MHz

VDD = 1.8V

—35

VDD = 2.5V/3.3V

Period Jitter

(Peak-to-Peak)

JPP

—70

—

fOUT =

27 MHz

VDD = 1.8V

—60

—

VDD = 2.5V/3.3V

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, VDD = 1.8V –5% to 3.3V +10%, TA = –40°C to +125°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Note 1: Pin 4 VDD should be filtered with 0.1 µF capacitor.

2: Not including current through pull-up resistor on EN pin (if configured). Higher standby current seen at

>3.3V VDD.

3: Includes frequency variations due to initial tolerance, temp. and power supply voltage.

4: Input waveform must be monotonic with rise/fall time < 10 ms

5: Output Disable time takes up to two periods of the output waveform + 200 ns.

6: For parts configured with OE, not Standby.

7: Output is enabled if pad is floated or not connected.

8: Time to reach 90% of target VDD. Power ramp rise must be monotonic.

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