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DSC6162JE2B-B bảng dữ liệu(PDF) 3 Page - Microchip Technology |
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DSC6162JE2B-B bảng dữ liệu(HTML) 3 Page - Microchip Technology |
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3 / 24 page ![]() 2019 Microchip Technology Inc. DS20006155A-page 3 DSC61XXB 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Supply Voltage .......................................................................................................................................... –0.3V to +4.0V Input Voltage (VIN) ..............................................................................................................................–0.3V to VDD+0.3V ESD Protection ............................................................................................................ 4 kV HBM, 400V MM, 2 kV CDM ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = 1.8V –5% to 3.3V +10%, TA = –40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Conditions Supply Voltage VDD 1.71 — 3.63 V Note 1 Power Supply Ramp tPU 0.1 — 100 ms Note 8 Active Supply Current IDD —3.0 — mA fOUT = 27 MHz, VDD = 1.8V, No Load Standby Supply Current ISTBY —1 — µA VDD = 1.8/2.5V, Note 2 —1.5 — VDD = 3.3V, Note 2 Output Duty Cycle SYM 45 — 55 % — Frequency f0 0.0035 — 100 MHz — Frequency Stability ∆f— — ±20 ±25 ±50 ppm All temp ranges, Note 3 Aging ∆f —— ±5 ppm 1st year @ 25°C — — ±1 Per year after first year Startup Time tSU —— 1.5 ms From 90% VDD to valid clock output, T = 25°C Input Logic Levels VIH 0.7 x VDD — — V Input Logic High, Note 4 VIL — — 0.3 x VDD V Input Logic Low, Note 4 Output Disable Time tDA —— 200 + 2 Periods ns Note 5 Output Enable Time tEN —— 1 µs Note 6 Enable Pull-up Resistor — — 300 — kΩ If configured, Note 7 Note 1: Pin 4 VDD should be filtered with 0.1 µF capacitor. 2: Not including current through pull-up resistor on EN pin (if configured). Higher standby current seen at >3.3V VDD. 3: Includes frequency variations due to initial tolerance, temp. and power supply voltage. 4: Input waveform must be monotonic with rise/fall time < 10 ms 5: Output Disable time takes up to two periods of the output waveform + 200 ns. 6: For parts configured with OE, not Standby. 7: Output is enabled if pad is floated or not connected. 8: Time to reach 90% of target VDD. Power ramp rise must be monotonic. |
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