TDC-GPX2 datasheet(39/77 Pages) AMSCO

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ams Datasheet

Page 39

[v1-03] 2017-Dec-18

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TDC-GPX2 − Detailed Description

RSTIDXP/N: Reference Index Counter Reset

With pin RSTIDX the internal counter for the reference index is

set back to zero. This option may simply the overview on the

reference index in the output data stream. RSTIDX is applied

synchronously to the reference clock for a single period.

Therefore one reference clock cycle passes, before stop events

are assigned with zero as reference index. The pin has to be

activated with PIN_ENA_RSTIDX.

Figure 40:

Reference Index Counter Reset

STOP1…STOP4P/N: Stop Channels

Inputs for the stop signals. The positive edges of the stop signals

are measured versus the preceding reference clock edge.

The chip has four independent stop channels. With CHANNEL_

COMBINE variations of this normal operation mode can be

achieved.

DISABLE/N: Stop Disable

With setting stop disable pin to HIGH, the measurement on all

four stops is disabled. The reference clock is not affected and

internal reference measurements are continued. The DISABLE

should meet the timing requirement with regards to a stop

event. The pin has to be activated by configuring PIN_ENA_

DISABLE to 1.

Input Levels, CMOS or LVDS

All input pins, STOP1 to STOP4, REFCLK, RSTIDX and DISABLE,

can be switched in common to CMOS input levels with CMOS_

INPUT configuration. Tie the unused negative inputs to

TVDD33.

REFCLK

RSTIDX

Reference

Index

N-2

N-1

N-2

N-1

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