RT8207LZQW datasheet(21/27 Pages) RICHTEK

21 / 27 page

DS8207L/M-08 September 2016

www.richtek.com

RT8207L/M

is a registered trademark of Richtek Technology Corporation.

Thermal Protection

The RT8207L/M monitors the temperature of itself. If the

temperature exceeds the threshold value, 165

°C (typ.),

the PWM output, VTTREF and VTT will be shut off. The

RT8207L/M is latched once thermal shutdown is triggered

and can only be released by VDD power on reset or S5.

Output Voltage Setting (FB)

The RT8207L/M can be used as DDR2 (VVDDQ = 1.8V)

and DDR3 (VVDDQ = 1.5V) power supply or as an adjustable

output voltage (0.75V < VVDDQ < 3.3V) by connecting the

FB pin according to Table 1.

Table 1. FB and output voltage setting

VDDQ (V)

VTTREF

and VTT

NOTE

VDD

1.8

VVDDQ / 2

DDR2

GND

1.5

VVDDQ /2

DDR3

Resistors

Adjustable VVDDQ / 2

0.75V < VVDDQ

< 3.3V

Connect a resistive voltage divider at FB between VDDQ

and GND to adjust the respective output voltage between

0.75V and 3.3V (Figure 8). Choose R2 to be approximately

10k

Ω and solve for R1 using the equation as follows :









VDDQ

REF

x 1

where VREF is 0.75V (typ.).

PHASE

LGATE

VVDDQ

VIN

UGATE

VDDQ

GND

Figure 8. Setting VDDQ with a Resistive Voltage Divider

VTT Linear Regulator and VTTREF

The RT8207L/M integrates a high performance low dropout

linear regulator that is capable of sourcing and sinking

currents up to 1.5A. This VTT linear regulator employs

ultimate fast response feedback loop so that small ceramic

capacitors are enough for keeping track of VTTREF within

40mV at all conditions, including fast load transient. To

achieve tight regulation with minimum effect of wiring

resistance, a remote sensing terminal, VTTSNS, should

be connected to the positive node of the VTT output

capacitor(s) as a separate trace from the VTT pin. For

stable operation, total capacitance of the VTT output

terminal can be equal to or greater than 20

μF. It is

recommended to attach two 10

μF ceramic capacitors in

parallel to minimize the effect of ESR and ESL. If ESR of

the output capacitor is greater than 2m

Ω, insert an RC

filter between the output and VTTSNS input to achieve

loop stability. The RC filter time constant should be almost

the same or slightly lower than the time constant made

by the output capacitor and its ESR. The VTTREF block

consists of on-chip 1/2 divider, LPF and buffer. This regulator

also has sink and source capability up to 10mA. Bypass

VTTREF to GND with a 33nF ceramic capacitor for stable

operation.

VDD sources the load of VTTREF to follow half voltage of

VDDQ. If VTTREF capacitor is so large that the VTTREF

is unable to follow half VDDQ voltage at time during soft

start period, VTTREF will sink large current from VDDwhich

causes large voltage drop at VDDP to VDD resistor and

has the opportunity of UVLO. The following equation

provides the maximum value of VTTREF capacitor

calculation.

VDDQ

VTTREF

VDD

VDDQ

OUT

VDDQ

OUT

VTTREF

VDDQ

VDD

0.03

= C

1.1 R

0.03 t

R2L

0.03

V1.1 R

0.03 t

R2L

















Where RVDD is the resistor between VDDP and VDD pin.

RDS is the turn on resistor of low-side MOSFET. CVTTREF

is the capacitor on the VTTREF pin. TSS is the soft start

time for VDDQ at the no load condition.

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