Rev. 1.0 / Nov. 2013

26

Input/Output Capacitance

Parameter

Symbol

DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866

Units Notes

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Input/output capacitance

(DQ, DM, DQS, DQS,

TDQS, TDQS)

1.4

2.5

1.4

2.5

1.4

2.3

1.4

2.2

1.4

2.1

pF

1,2,3

Input capacitance, CK and

CK

0.8

1.6

0.8

1.6

0.8

1.4

0.8

1.4

0.8

1.3

pF

2,3

Input capacitance delta

CK and CK

0

0.15

0

0.15

0

0.15

0

0.15

0

0.15

pF

2,3,4

Input capacitance delta,

DQS and DQS

0

0.20

0

0.20

0

0.15

0

0.15

0

0.15

pF

2,3,5

Input capacitance

(All other input-only pins)

0.75

1.3

0.75

1.3

0.75

1.3

0.75

1.2

0.75

1.2

pF

2,3,6

Input capacitance delta

(All CTRL input-only pins)

L

-0.5

0.3

-0.5

0.3

-0.4

0.2

-0.4

0.2

-0.4

0.2

pF

2,3,7,8

Input capacitance delta

(All ADD/CMD input-only

pins)

_CMD

-0.5

0.5

-0.5

0.5

-0.4

0.4

-0.4

0.4

-0.4

0.4

pF

2,3,9,10

Input/output capacitance

delta

(DQ, DM, DQS, DQS)

-0.5

0.3

-0.5

0.3

-0.5

0.3

-0.5

0.3

-0.5

0.3

pF

2,3,11

Input/output capacitance

of ZQ pin

-

3

-

3

-

3

-3-3

pF

2,3,12

Notes:

1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.

2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured

according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”)

with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as neces-

sary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

12. Maximum external load capacitance an ZQ pin: 5 pF.