PIN 1

BASE

(INPUT)

PIN 3

COLLECTOR

(OUTPUT)

PIN 2

EMITTER

(GROUND)

R

1

R

2

NPN Silicon Surface Mount Transistor

with Monolithic Bias Resistor Network

This new series of digital transistors is designed to replace a single

device and its external resistor bias network. The BRT (Bias Resistor

Transistor) contains a single transistor with a monolithic bias network

consisting of two resistors; a series base resistor and a base-emitter

resistor. The BRT eliminates these individual components by

integrating them into a single device. The use of a BRT can reduce

both system cost and board space. The device is housed in the SC-70 /

SOT-323 package which is designed for low power surface mount

applications.

Simplifies Circuit Design

•

Reduces Board Space

•

Reduces Component Count

•

Rating

Symbol

Value

Unit

Collector-Base Voltage

50

Vdc

Collector-Emitter Voltage

50

Vdc

Collector Current

I

C

100

mAdc

THERMAL CHARACTERISTICS

Characteristic

Symbol

Max

Unit

Total Device Dissipation

Derate above 25 C

202 (Note 1.)

310 (Note 2.)

1.6 (Note 1.)

2.5 (Note 2.)

mW

mW/ C

Thermal Resistance –

Junction-to-Ambient

618 (Note 1.)

403 (Note 2.)

C/W

Thermal Resistance –

Junction-to-Lead

280 (Note 1.)

332 (Note 2.)

C/W

Junction and Storage

Temperature Range

–55 to +150

C

1. FR–4 @ Minimum Pad

2. FR–4 @ 1.0 x 1.0 inch Pad

SC-70 / SOT-323

Bias Resistor Transistors

2008. 03. 10

1/10

SEMICONDUCTOR

TECHNICAL DATA

DTC301~311 / DTC317

DTC322~323

Revision No : 0

DEVICE MARKING INFORMATION

See specific marking information in the device marking table on

page 2 of this data sheet.

3

2

1