© VITESSE SEMICONDUCTOR CORPORATION

Page 3

12/1/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8151

2.488Gb/s SONET/SDH

STS-48/STM-16 Section Terminator

G52225-0, Rev. 2.9

The serial demux can be bypassed and the 16-bit single-ended PECL bus RXPIN[15:0] can be used to input

SONET/SDH data for applications where the data has already been deserialized by a previous device. This

mode is selected by asserting the EQULOOP input (active high). Input setup and hold requirements are speci-

fied with respect to the falling edge of POUTCLK; the user is responsible for meeting loop timing requirements

between the VSC8151 and previous device. The user must still provide a line rate clock to the serial clock input

RXSLKIN+/- to provide a high-speed output clock to the mux and the means to create the divide-by-16 POUT-

CLK.

2.5G Serial and Parallel Output Interfaces

The high speed clock and data output driver consists of a differential pair designed to drive a 50

Ω transmis-

sion line. The transmission line should be terminated with a 100

Ω resistor at the load between true and comple-

ment outputs. No connection to a termination voltage is required. The output driver is source terminated to 50

Ω

on-chip, providing a snubbing of any reflections. If used single-ended, one way to terminate the output driver is

differentially at the load with a 100

Ω resistor between true and complement outputs. See Figure 2A. Another

In some applications, it may be desirable to turn off the high speed outputs (TXSOUT, TXSCLKOUT) to

current consumption by 107mA for the clock output, and 122mA for the data output.

Figure 2: High Speed Output Driver & Termination

50

Ω

100

Ω

50

Ω

Pre-Driver

Figure 2A

50

Ω

50

Ω

50

Ω

50

Ω

Pre-Driver

Figure 2B