LXT975B datasheet(63/74 Pages) INTEL

63 / 74 page

Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975

Datasheet

5.0

The LXT974/975 register set includes a total of 48 16-bit registers, 12 registers per port. Refer to

Table 43 for a complete register listing.

• Seven base registers (0 through 6) are defined in accordance with the “Reconciliation Sublayer

and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-

Negotiation” sections of the IEEE 802.3 specification (Register 7, Next Page, is not

supported).

• Five additional registers (16 through 20) are defined in accordance with the IEEE 802.3

specification for adding unique chip functions.

Table 43. Register Set

Address

Bit Assignments

Control Register

Refer to Table 44 on page 64

Status Register

Refer to Table 45 on page 65

PHY Identification Register 1

Refer to Table 46 on page 66

PHY Identification Register 2

Refer to Table 47 on page 66

Auto-Negotiation Advertisement Register

Refer to Table 48 on page 67

Auto-Negotiation Link Partner Ability Register

Refer to Table 49 on page 67

Auto-Negotiation Expansion Register

Refer to Table 50 on page 68

LED Configuration Register

Refer to Table 51 on page 68

Interrupt Enable Register

Refer to Table 52 on page 69

Interrupt Status Register

Refer to Table 53 on page 70

Port Configuration Register

Refer to Table 54 on page 70

Port Status Register

Refer to Table 55 on page 71

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