LM2502 datasheet(23/27 Pages) NSC

23 / 27 page

Application Information (Continued)

DISPLAY APPLICATION

The LM2502 chipset is intended for Interface between a host

(processor) and a Display. It supports a 16 or 8-bit CPU style

interface and can be configured for i80 or m68 modes.

The Master side connection is shown in Figure 19. Input

Clock frequency and the selection of the PLL_CON setting

are determined by system parameters. These include the

required display bandwidth, the Master load rate and the

Display Driver input timing requirements. See the System

Considerations section for more details.

The Display side parallel bus may be connected to one or

two displays. Each display has its own chipselect signal. If

only one display is required, the unused CS signal should be

tied HIGH (V

DDIO) on the Master, and the unused output left

open on the Slave. The Slave provides an optional clock

output. If this is desired the CLKDIS* pin needs to be also

tied HIGH. A different PLL_CON setting can be used to alter

the frequency if desired. As the Divisor setting in the Slave is

not used for data recovery. For the dual display application,

the multidrop bus should be laid out to minimize any result-

ing stub lengths on the Data, A/D, and control signals.

If required, the Slave output clock can be enabled to provide

a output frequency reference. The frequency can be ad-

justed by setting different PLL_CON (divisor) settings (on the

Slave). This can then be used as a frequency reference

signal to the display module or other subsystem (ie camera

module). If the CLK output is not needed, tie the Slave

CLKDIS* pin Low to disable it. The Clock is available when

ever the MPL link is enabled.

20093321

FIGURE 18. LM2502 UFBGA Package PWR (V

DD) and GND (VSS) Balls

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