VSP2272

SLES020 – DECEMBER 2001

8

www.ti.com

timing specifications (continued)

VSP2272 serial interface

SLOAD

SCLK

SDATA

tw(CKH)

t(CKP)

MSB

LSB

tsu(X)

th(X)

tw(CKL)

tsu(D)

th(D)

2 Bytes

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

t(CKP)

Clock period

100

ns

tw(CKH)

Clock high pulse width

40

ns

tw(CKL)

Clock low pulse width

40

ns

tsu(D)

Data setup time

30

ns

th(D)

Data hold time

30

ns

tsu(X)

SLOAD to SCLK setup time

30

ns

th(X)

SCLK to SLOAD hold time

30

ns

NOTES: 12. Data shift operation must decode at the rising edges of SCLK while SLOAD is low. Two bytes of input data are loaded to the parallel

latch in the VSP2272 device at the rising edge of SLOAD.

13. When the input serial data is longer than 2 bytes (16 bits), the last 2 bytes become effective and the former bits are lost.