CY28317PVC-2 datasheet(7/21 Pages) CYPRESS

7 / 21 page

CY28317-2

Document #: 38-07094 Rev. *B

Page 7 of 21

Byte 3: Control Register 3

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

Bit 6

–

SEL_48MHz

0 = 24 MHz

1 = 48 MHz

Bit 5

48MHz

(Active/Inactive)

Bit 4

24_48MHz

(Active/Inactive)

Bit 3

–

Reserved

Bit 2

31, 30

SDRAM4:5

(Active/Inactive)

Bit 1

34, 33

SDRAM2:3

(Active/Inactive)

Bit 0

37, 36

SDRAM0:1

(Active/Inactive)

Byte 4: Control Register 4

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

Bit 6

–

Reserved

Bit 5

–

Reserved

Bit 4

–

Reserved

Bit 3

–

Reserved

Bit 2

–

Reserved

Bit 1

–

Reserved

Bit 0

–

Reserved

Byte 5: Control Register 5

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

Bit 6

–

Reserved

Bit 5

–

Reserved

Bit 4

–

CPU1

Stop Control

0 = CPU1 will be stopped when

CPU_STOP# is active

1 = CPU1 will NOT be stopped when

CPU_STOP# is active

Bit 3

–

CPU0

Stop Control

0 = CPU0 will be stopped when CPU_STOP# is active

1 = CPU0 will NOT be stopped when CPU_STOP# is

active

Bit 2

–

CPUT and

CPUC Stop

Control

0 = CPUT and CPUC will be stopped when

CPU_STOP# is active

1 = CPUT and CPUC will NOT be stopped when

CPU_STOP# is active

Bit 1

REF1

(Active/Inactive)

Bit 0

REF0

(Active/Inactive)

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