ADF41513 datasheet(5/30 Pages) AD

tên linh kiện	ADF41513

Giải thích chi tiết về linh kiện	26.5 GHz, Integer N/Fractional-N, PLL Synthesizer

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5 / 30 page

Data Sheet

ADF41513

Rev. 0 | Page 5 of 30

TIMING CHARACTERISTICS

AVDDx = AVDD1 = AVDD2 = AVDD3 = AVDD4 = AVDD5 = VP = 3.3 V ± 5%, GND = 0 V, RSET = 1.8 kΩ, dBm referred to 50 Ω, TA = TMIN (−40°C)

to TMAX (+105°C), unless otherwise noted.

Table 2. Read and Write Timing

Parameter

Limit at TMIN to TMAX

Unit

Test Conditions/Comments

ns min

LE setup time

ns min

DATA to CLK setup time

ns min

DATA to CLK hold time

12.5

ns min

CLK high duration

12.5

ns min

CLK low duration

ns min

CLK to LE setup time

ns min

LE pulse width

ns max

LE setup time to MUXOUT when MUXOUT is configured as SPI output

ns max

CLK setup time to MUXOUT when MUXOUT is configured as SPI output

Timing Diagram

CLK

DATA

DB30

DB1

(CONTROL BIT C2)

DB2

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

DB31 (MSB)

DB0

DB1

DB31

(MSB)

DB30

MUXOUT

Figure 2. Read and Write Timing

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