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Slave

The device addressed by the host

Multi-master

At the same time there is more than one host attempts to control the bus, but do

not destroy the message

Arbitration

There is a multiple hosts at the same time try to control the bus, but only allows

it a control bus and make the message is not destroyed in the process

Synchronous

Two or more devices in the process of synchronizing the clock signal

◎Data validity

Data line SDA data must remain stable during the high period of the clock. High or low state

of the data line SDA is only in the low period of SCL clock line only allowed to change. But at the

start and end I C bus exceptions (for details see the start and stop conditions). Some other serial bus

data as may be required valid edge (rising or falling) of the clock signal, but I C bus is valid level.

The specific timing diagram shown in Figure 6.

Figure 6: Bit Transfer

C bus

◎Start and stop conditions

Start condition: Period when SCL is high, SDA high to low Start condition generating

transition from. Bus after the start condition is generated in a busy state. The

initial condition is often abbreviated as S.

Stop condition: Period when SCL is high, SDA generates a stop condition low to high

transition from. Bus stop condition is generated in an idle state. The stop

condition abbreviated as P.

Start and stop conditions diagram shown in Figure 7.

Figure 7: Schematic start and stop conditions

◎Byte transfer format

I C bus to send and receive data in bytes. Each byte is transmitted to the SDA line must be 8.

The number of bytes per transfer is unrestricted. First, is the highest transmission bit data (MSB bit

2

2

2

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