GD25LE256DWJS datasheet(35/83 Pages) GIGADEVICE

35 / 83 page

1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LE256D

7.14. Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest

address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure15. The first

byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte

of data is shifted out. The default read mode is 3-byte address mode, and the lower 128Mbit can be read with a single Quad

I/O Word Fast Read (E7H) command. By entering 4-byte address mode, or to set EN4B (S11) bit to 1, the higher 128Mbit

can be read with a single Quad I/O Word Fast Read (E7H) command. The Quad Enable bit (QE) of Status Register (S9)

must be set to enable for the Quad I/O Word Fast read command.

Quad I/O Word Fast Read with

“Continuous Read Mode”

The Quad I/O Word Fast Read command can further reduce command overhead through setting the

“Continuous

Read Mode

” bits (M7-0) after the input 3-byte address (A23-A0) or a 4-byte address (A31-A0). If the “Continuous Read

Mode

” bits (M5-4) = (1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does

not require the E7H command code. The command sequence is shown in followed Figure15. If the

“Continuous Read Mode”

bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus returning to normal operation.

Figure15. Quad I/O Word Fast Read Sequence Diagram (M5-4

≠ (1, 0))

Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.

Figure15a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))

Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.

CS#

SCLK

9 10 11 12 13 14 15

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

A23-16 A15-8 A7-0

M7-0 Dummy Byte1 Byte2

Byte3

Command

E7H

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A23-16 A15-8 A7-0

M7-0

WP#(IO2)

HOLD#(IO3)

Dummy

Byte1 Byte2

Byte3

GD25LE256DWJS bảng dữ liệu(PDF) 35 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25LE256DWJS bảng dữ liệu(HTML) 35 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

bảng dữ liệu tải về

Link URL