GD25LE256DWJS datasheet(32/83 Pages) GIGADEVICE

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1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LE256D

7.13. Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the

3-byte address (A23-0) or a 4-byte address (A31-A0) and a

“Continuous Read Mode” byte and 4-dummy clock 4-bit per

clock by IO0, IO1, IO3, IO4, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out

4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure14. The first byte

addressed can be at any location. The address is automatically incremented to the next higher address after each byte of

data is shifted out. The default read mode is 3-byte address mode, and the lower 128Mbit can be read with a single Quad

I/O Fast Read (EBH) command. By entering 4-byte address mode, or to set EN4B (S11) bit to 1, the higher 128Mbit can be

read with a single Quad I/O Fast Read (EBH) command. The Quad Enable bit (QE) of Status Register (S9) must be set to

enable for the Quad I/O Fast read command.

Figure14. Quad I/O Fast Read Sequence Diagram (M5-4

≠ (1, 0))

Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.

Command

EBH

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A23-16 A15-8 A7-0

M7-0

WP#(IO2)

HOLD#(IO3)

Dummy

Byte1 Byte2

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