GD25LE80CLIGR datasheet(27/68 Pages) GIGADEVICE

27 / 68 page

1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LE80C

7.15 Sector Erase (SE) (20H)

The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command must

previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by

driving CS# low, followed by the command code, and 3-address Byte on SI. Any address inside the sector is a valid address

for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.

The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-Byte address on SI  CS#

goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of the last address Byte

has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-

timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register

may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed

Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable

Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4,

BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.

Figure 18. Sector Erase Sequence Diagram

Command

20H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

7.16 32KB Block Erase (BE) (52H)

The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command

must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is

entered by driving CS# low, followed by the command code, and three address Bytes on SI. Any address inside the block

is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.

The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-Byte address on

SI  CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of the last

address Byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is

driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in progress,

the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1

during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is

protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.

Figure 19. 32KB Block Erase Sequence Diagram

Command

52H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

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