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3. Functional Description

This chapter describes the functions integrated in ESP32.

3.1 CPU and Memory

3.1.1 CPU

ESP32 contains one or two low-power Xtensa® 32-bit LX6 microprocessor(s) with the following features:

• 7-stage pipeline to support the clock frequency of up to 240 MHz (160 MHz for ESP32-S0WD and ESP32-

D2WD)

• 16/24-bit Instruction Set provides high code-density

• Support for Floating Point Unit

• Support for DSP instructions, such as a 32-bit multiplier, a 32-bit divider, and a 40-bit MAC

• Support for 32 interrupt vectors from about 70 interrupt sources

The single-/dual-CPU interfaces include:

• Xtensa RAM/ROM Interface for instructions and data

• Xtensa Local Memory Interface for fast peripheral register access

• External and internal interrupt sources

• JTAG for debugging

3.1.2 Internal Memory

ESP32’s internal memory includes:

• 448 KB of ROM for booting and core functions

• 520 KB of on-chip SRAM for data and instructions

• 8 KB of SRAM in RTC, which is called RTC FAST Memory and can be used for data storage; it is accessed

by the main CPU during RTC Boot from the Deep-sleep mode.

• 8 KB of SRAM in RTC, which is called RTC SLOW Memory and can be accessed by the co-processor during

the Deep-sleep mode.

• 1 Kbit of eFuse: 256 bits are used for the system (MAC address and chip configuration) and the remaining

768 bits are reserved for customer applications, including flash-encryption and chip-ID.

• Embedded flash

Note:

• Products in the ESP32 series differ from each other, in terms of their support for embedded flash and the size of it.

For details, please refer to Part Number and Ordering Information.

• ESP32-D2WD has a 16-Mbit, 40-MHz embedded flash, connected via pins GPIO16, GPIO17, SD_CMD, SD_CLK,

SD_DATA_0 and SD_DATA_1.

Espressif Systems

ESP32 Datasheet V3.0

ESP32 bảng dữ liệu(PDF) 20 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.