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NM148F2KSLAXCL bảng dữ liệu(PDF) 40 Page - Nanya Technology Corporation.

tên linh kiện NM148F2KSLAXCL
Giải thích chi tiết về linh kiện  MCP Specification
PDF  121 Pages
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NM148F2KSLAXCL bảng dữ liệu(HTML) 40 Page - Nanya Technology Corporation.

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Version 1.6
40
Nanya Technology Corp.
05/2018
All Rights Reserved. ©
4Gb SLC NAND + 2Gb LPDDR2
NM148(F)2KSLAXCL/NM1482NSLAXCL
NTC Proprietary
Level: Property
For X8 :
For X16 :
10 Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input.
11 By issuing the 10h command, the data in the Page Buffer is programmed to Page M + Rn.
(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG here will be expected
as the following,
tPROG = tPROG of the last page + tPROG of the previous page − ( command input cycle + address input cycle + data output/input cycle
time of the last page)
NOTE) This operation needs to be executed within District-0 or District-1.
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and
change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
Make sure
 is held to High level when Page Copy (2) operation is performed.
Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence



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