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M29DW128F bảng dữ liệu(PDF) 36 Page - STMicroelectronics

tên linh kiện M29DW128F
Giải thích chi tiết về linh kiện  128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
PDF  93 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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M29DW128F bảng dữ liệu(HTML) 36 Page - STMicroelectronics

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6 Command Interface
M29DW128F
36/93
6.2.10 Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in the memory
array at a time. The command requires two Bus Write operations, the final write operation
latches the address and data and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass Program command behaves identically to the
Program operation using the Program command. The operation cannot be aborted, a Bus
Read operation to the Bank where the command was issued outputs the Status Register. See
the Program command for details on the behavior.
6.2.11 Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock
Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass Reset
command. Read/Reset command does not exit from Unlock Bypass mode.
Table 13.
Fast Program Commands, 8-bit mode
Command
Bus Write Operations(1)
1.
X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address, WBL Write Buffer Location. All
values in the table are in hexadecimal.
1st
2nd
3rd
4th
5th
6th
7th
8th
9th
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Write to Buffer
and Program
N
+
5
AAA
AA
555
55
BA
25
BA
N(2)
2.
The maximum number of cycles in the command sequence is 37. N+1 is the number of Words to be programmed during the Write to Buffer
and Program operation.
PA
(3)
3.
Each buffer has the same A5-A22 addresses. A0-A4 are used to select a Word within the N+1 Word page.
PD
WBL
(4)
4.
The 6th cycle has to be issued N time. WBL scans the Word inside the page.
PD
Write to Buffer
and Program
Abort and
Reset
3
AAA
AA
555
55
AAA
F0
Write to Buffer
and Program
Confirm
1
BA
(5)
5.
BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles.
29
Double Byte
Program
3
AAA
50
PA0
PD0
PA1
PD1
Quadruple Byte
Program
5
AAA
56
PA0
PD0
PA1
PD1
PA2
PD2
PA3
PD3
Octuple Byte
Program
9
AAA
8B
PA0
PD0
PA1
PD1
PA2
PD2
PA3
PD3
PA4
PD4
PA5
PD5
PA6
PD6
PA7
PD7
Unlock Bypass
3
AAA
AA
555
55
AAA
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass
Reset
2X
90
X
00



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