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RF64W bảng dữ liệu(PDF) 72 Page - HOPE Microelectronics CO., Ltd. |
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RF64W bảng dữ liệu(HTML) 72 Page - HOPE Microelectronics CO., Ltd. |
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72 / 76 page ![]() ADVANCED COMMUNICATIONS & SENSING Page 72 of 76 RF64 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 7.4. Reset of the Chip A power-on reset of the RF64 is triggered at power up. Additionally, a manual reset can be issued by controlling pin 13. 7.4.1. POR If the application requires the disconnection of VDD from the RF64, despite of the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 13 (TEST8) should be left floating during the POR sequence. VDD Pin 13 (output) Undefined Wait for 10 ms Chip is ready from this point on Figure 54: POR Timing Diagram Please note that any CLKOUT activity can also be used to detect that the chip is ready. 7.4.2. Manual Reset A manual reset of the RF64 is possible even for applications in which VDD cannot be physically disconnected. Pin 13 should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the chip. Figure 55: Manual Reset Timing Diagram Please note that while pin 13 is driven high, an over current consumption of up to ten milliamps can be seen on VDD. |
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