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MSM82C59A-2RS/GS/JS

(17) Special Fully Nested Mode

This mode is used in large systems where the cascade mode is used and the respective

Interrupt Requests within each slave have to be given priority levels. In this case, the

Special Fully Nested mode is programmed to the master by using ICW4. This mode is

practically identical to the normal Fully Nested mode, but differs in the following two

respects.

a. When an interrupt request is received from a particular slave during servicing, a new

interrupt request from an IR with a higher priority level than the interrupt level of the

slave being serviced is recognized by the master and the interrupt is applied to the

processor without the master priority logic being inhibited by the slave. In normal

Fully Nested mode, if the request is in service, a slave is masked and no other requests

can be recognized from the same slave.

b. When exiting from an interrupt service routine, it is first necessary to check whether

or not the interrupt which has just been serviced by soft ware was the only interrupt

from that slave. This is done by sending a Non-Specific EOI command to that slave,

followed by reading of the In-Service Register (ISR) to see whether that register has

become all ‘0’. A Non-Specific EOI is sent to the master too if the ISR is empty, and if

not no EOI should be sent.

(18) Buffered Mode

Control for buffer enabling is required when the MSM82C59A-2 is used in a large system

where a data bus drive buffer is needed and cascade mode is used. When buffered mode

is selected, the MSM82C59A-2 sends an enable signal on the SP/EN pin to enable the

buffer. In this mode, the SP/EN output always becomes active while the MSM82C59A-

2’s data bus output is enabled. Therefore, the MSM82C59A-2 requires programming to

enable it to distinguish master from slave. Buffered mode is programmed by bit 3 in ICW4,

and the ability to distinguish master from slave is programmed by bit 2 in ICW4.

(19) Cascade Mode

To enable the MSM82C59A-2 to handle up to 64 priority levels, a maximum of 8 slaves can

be easily connected to one master device.

The master controls the slaves through three cascade lines, the cascade bus executes like

a slave chip select during the INTA sequence.

In cascade configuration, slave interrupt outputs (INT) are connected to master interrupt

request inputs (IR). When a slave IR becomes active and is acknowledged, the master

enables the corresponding slave to release the routine address for that device during bytes

2 and 3 (only byte 2 in 86 mode) of the INTA sequence.

The cascade bus line is normally kept at low level, and holds the slave address during the

period from the rising edge of the first INTA pulse up to the rising edge of the thirdINTA

pulse (or the second INTA pulse in 86 mode).

Each MSM82C59A-2 device in the system can operate in different modes in accordance

with their initialization sequences. EOI commands must be issued twice, once for the

master once for the corresponding slave. Each MSM82C59A-2 requires an address

decoder to activate the respective chip select (CS) inputs.

Since the cascade line is normally kept at low level, note that slaves must be connected to