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MSM82C59A-2RS/GS/JS

(15) Reading MSM82C59A-2 Status

The status of a number of internal registers can be read out for updating user information

on the system. The following registers can be read by means of OCW3 (IRR and ISR) and

OCW1 (IMR).

a. IRR: (Interrupt Request Register) 8-bit register for storing interrupt requesting levels.

b. ISR: (In-Service Register) 8-bit register for storing priority levels being serviced.

c. IMR: (Interrupt Mask Register) 8-bit register for storing interrupt request lines to be

masked.

The IRR can be read when a Read Register Command is issued with OCW3 (RR = 1 and

RIS = 0) prior to the RD pulse, and the ISR can be read when a Read Register command is

issued with OCW3 (RR = 1 and RIS = 1) prior to the RD pulse. And as long as the read status

does not change, OCW3 is not required each time before the status is read. This is because

the MSM82C59A-2 remembers whether IRR or ISR was selected by the previous OCW3.

But this is not true when poll is used.

The MSM82C59A-2 is set to IRR after initialization. OCW3 is not required to read IMR.

Reading status is disabled by polling when P = 1 and RR = 1 in OCW3.

(16) Edge and Level Trigger Mode

This mode is programmed by using bit 3 (LTIM) in ICW1. When LTIM = 0, the interrupt

request is recognized by the IR input transition from Low to High. As long as the IR input

is kept at High, no other interrupt is generated. Since interrupt requests are recognized

by the IR input “H” level when LTIM = 1, edge detection is not required.

The interrupt request must be cancelled before output of the EOI command, and before the

interrupt is enabled in order to prevent the generation of a second interrupt by the CPU.

The IR input must be held at High level until the falling edge of the first INTA pulse,

irrespective of whether edge sense or level sense is employed. If the IR input is switched

to Low level before the first INTA pulse, the default IR7 is generated when the interrupt

is acknowledged by the CPU. This can be an effective safeguard to be adopted to detect

interrupts generated by the noise glitches on the IR inputs. To take advantage of this

feature, the IR7 routine is used as a “clean up” routine where the routine is simply

executing a return instruction and the interrupt is subsequently ignored. When the IR7 is

required for other purposes, the default IR7 can be detected by reading the ISR. Although

correct IR7 interrupts involve setting of the corresponding ISR bit, the default IR7 is not

set.

IR7 routine

IS7=1?

IR7 service

processing

EOI

No

Yes

RETURN

(IR noise

detection)