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MSM82C37B-5RS/GS/VJS

DESCRIPTION OF INTERNAL REGISTERS

Current Address Register

Each channel is equipped with a 16-bit long current address register where the transfer address

is held during DMA transfers. The register value is incremented (or decremented) in each DMA

cycle. Although this register is 16 bits long, the CPU is accessed by the MSM82C37B-5 eight bits

at a time, therefore necessitating two successive 8-bit (lower and higher order bits) reading or

writing operations using internal first/last flip-flops.

When autoinitialize has been set, the register is automatically initialized to the original value

after TC.

Current Word Count Register

Each channel is also equipped with a 16 bit-long current word count register where the transfer

count is held during DMA transfers. The register value is decremented in each DMA cycle.

When the word count value reaches FFFF(H) from 0000(H), a TC is generated. Therefore, a word

count value which is one less than the actual number of transfers must be set.

Since this register is also 16 bits long, it is accessed by first/last flip-flops control in the same way

as the address register. And if autoinitialize has been set, the register is automatically initialized

to the original value after TC.

Base Address Register and Base Word Count Register

Each channel is equipped with a 16-bit long base address register and base word count register

where the initial value of each current register is held. The same values are written in each base

register and the current register by the CPU. The contents of the current register can be made

ready by the CPU, but the content of the base register cannot be read.