18/20

¡ Semiconductor

MSM80C48/49/50, MSM80C35/39/40

4.3 Hardware power-down mode

during either external ROM or internal ROM mode results in suspension of the oscillator

function and subsequent floating (high impedance) of all the I/O pins except the RESET,

SS and XTAL 1/2 pins. The CPU is thereby stopped while maintaining internal status.

4.4 Cancellation of hardware power-down mode

(1) Use of RESET pin

m

The clock generator is activated and the CPU started up when a "1" level is applied to

to the RESET pin until oscillation become stable, the CPU will be reset and will start

executing from address 0.

(2) Use of the INT pin during external interrupt enable status (i.e. following execution of EN

I instruction)

m

The clock generator is activated and the CPU started up when a "1" level is applied to

until the occurrence of at least 2 ALE output signals, an external interrupt is generated,

and execution starts from address 3.

However, if the power-down mode is started during an interrupt processing routine,

execution will be continued on the next instruction after the present instruction.

(3) Use of the INT pin during external interrupt disable mode (i.e. following excution of DIS

I instruction or hardware reset)

m

The clock generator is activated and the CPU started up when a "1" level is applied to

until the occurrence of at least 2 ALE output signals, execution is continued on the next

instruction after the present instruction.

m

The clock generator is activated and the CPU started up when a "1" level is applied to

case, execution is resumed from the stopped position.