AD9958

Rev. 0 | Page 34 of 40

CONTROL REGISTER MAP

REGISTER MAPS

Table 27.

Register

Name

(Address)

Bit

Range

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

Channel

Select

Register

(CSR)

(0x00)

<7:0>

Channel 1

Channel 0

enable

1

Open

Open

Must be

0

Serial I/0 mode select <2:1>

LSB first

0xF0

Function

Register 1

(FR1)

(0x01)

<7:0>

Reference clock

input power

down

External power

down mode

Sync clock

disable

DAC reference

power down

Open

Open

Manual

hardware

synchronization

Manual

software

synchronization

0x00

<15:8>

Open

Profile pin configuration <14:12>

Ramp up/ramp

down <11:10>

Modulation Level <9:8>

0x00

<23:16>

VCO gain

control

PLL divider ratio <22:18>

Charge pump control <17:16>

0x00

Function

Register

Two (FR2)

(0x02)

<7:0>

Multi-device

synchronization

slave enable

Multi-device

synchronization

master enable

Multi-device

synchronization

status

Multi-device

synchronization

mask

Open <3:2>

System clock offset <1:0>

0x00

<15:8>

Both channels

auto clear

sweep

accumulator

Both channels

clear sweep

accumulator

Both channels

auto clear

phase

accumulator

Both channels

clear phase

accumulator

Open <11:10>

Open <9:8>

0x00

I/O update to become active. The two channel enable bits shown in the register map are used to enable/disable any combination of the four channels. Both channels’

default are enabled.

In the CSR register, if the user wants different frequencies for both DDS channels, the following protocol suffices.

1.

Enable (Logic 1) the CH0 bit, which is located in the channel select register and disable the CH1 enable bit (Logic 0).

2.

Write the desired frequency tuning word for CH0, as described in Step 1.

3.

Disable CH0 enable bit (Logic 0) and enable the CH1 bit in the channel select register.

4.

Write the desired frequency tuning word for CH1.