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EM5305VT bảng dữ liệu(PDF) 11 Page - Excelliance MOS Corp. |
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EM5305VT bảng dữ liệu(HTML) 11 Page - Excelliance MOS Corp. |
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11 / 12 page ![]() 2013/7/11 A.2 11 EM5305 Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFET. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the upper MOSFET turn on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of the upper MOSFET and the source of the lower MOSFET. The important parameters of the input capacitor are the voltage rating and the RMS current rating. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement can be expressed as the following equation: D) - D(1 I I OUT RMS = For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can also be used but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. Power MOSFET Selection The EM5305 requires two N-Channel power MOSFETs. These should be selected based upon on-resistance, breakdown voltage, gate supply requirement, and thermal management requirements. In high current applications, the MOSFET power dissipation, package selection and heat sink are the dominate design factor. The power dissipation includes two loss components: conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The power dissipations in the two MOSFETs are approximately the following equation: SW SW IN OUT DS(ON) OUT 2 UPPER t F V I D * R * I PD * * * * 5 . 0 + = D) - (1 * R * I PD DS(ON) OUT 2 LOWER = Where D is the duty cycle, tSW is the combined switch ON and OFF time. |
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