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M65818AFP bảng dữ liệu(PDF) 34 Page - Renesas Technology Corp

tên linh kiện M65818AFP
Giải thích chi tiết về linh kiện  Digital Amplifier Processor of S-Master Technology
PDF  39 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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M65818AFP bảng dữ liệu(HTML) 34 Page - Renesas Technology Corp

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M65818AFP
Rev.1.00, Sep.04.2003, page 34 of 38
• ∆ΣBlock: AC dithering Rch Phase (bit21: ACDRPOL).
"L"…Same phase
"H"…Reverse phase
• ∆Σ Block: AC dithering Selection (bit22,bit23,bit24: ACDSEL0,ACDSEL1,ACDSEL2).
Refer to Table 6-3-3.
7.1. AC Characteristics Lists.
(Ta=25
°C, PWM Vdd=5V, DVdd=3.3V)
AC Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
XfsoIN duty ratio
duty(XfsoIN)
40
50
60
%
XfsiIN duty ratio
duty(XfsiIN)
512fsi
30
50
70
%
256fsi
40
50
60
nsec
SCSHIFT pulse time
tw(SCSHIFT)
160
nsec
SCDT setup time
tsu(SCDT)
80
nsec
SCDT hold time
th(SCDT)
80
nsec
SCLATCH pulse width
tw(SCLATCH)
160
nsec
SCLATCH setup time
tsu(SCLATCH)
160
nsec
SCLATCH hold time
th(SCLATCH)
160
nsec
BCK pulse width
tw(BCK)
35
nsec
DATA setup time
tsu(DATA)
20
nsec
DATA hold time
th(DATA)
20
nsec
LRCK setup time
tsu(LRCK)
20
nsec
LRCK hold time
th(LRCK)
20
nsec
EXBCK pulse time
tw(EXBCK)
35
nsec
EXWCK setup time
tsu(EXWCK)
20
nsec
EXWCK hold time
th(EXWCK)
20
nsec
EXDATA L / R setup time
tsu(EXDATA)
20
nsec
EXDATA L / R hold time
th(EXDATA)
20
nsec
EXDATA L / R output delay time
tpd(EXDATA)
Output load capacity 10 [pF]
1.0
nsec
EXWCK output delay time
tpd(EXWCK)
Output load capacity 10 [pF]
1.0
nsec
DSD128fs pulse width
tw(DSDCK128)
70
nsec
DSD64fs pulse width
tw(DSDCK64)
140
nsec
DSD64fs setup time
tsu(DSDCK64)
mode 1, 3
40
nsec
DSD64fs hold time
th(DSDCK64)
mode 1, 3
40
nsec
DSD L / R setup time
tsu(DATA)
mode 1, 2, 3, and 4
40
nsec
DSD L / R hold time
th(DATA)
mode 1, 2, 3, and 4
40
nsec
SYNC pulse width
tw(SYNC)
160
nsec



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