CLC503 datasheet(5/6 Pages) NSC

5 / 6 page

Pin 1

Power Down (PDN): The power down pin takes

CMOS input levels.

Use this to decrease the

power from 250mW to 40mW.

This is not a

signal disable pin. A CMOS gate will drive this

input. The quiescent supply current will be

decreased when PDN is at least 1V higher than

Vcm. When the current is turned off, the output

voltage Vo, will go to approximately 4.3V. An

internal pull down resistor of 10k allows PDN to

be left open when not used.

Pin 2

Input Voltage (Vin): This is the signal input. The

recommended input range is ±1V.

The linear

operating range is approximately ±1.4V

This

input controls the differential output voltage.

Because of the closed loop nature of the trans-

conductance stage, the transfer function is highly

linear. Refer to

Output Voltage pin for output

signal limitations.

Pin 3

Ground (GND): Tie to low impedance analog

ground.

Pins 4 and 5

Power Supplies (VEE and VCC): For optimum

performance, use linear ±5V power supplies.

Use bypass capacitors of 0.1

µF and 6.8µF on the

power supply lines to decrease any noise that

could be injected into the circuit by the power

supplies. Place the bypass capacitors as close

to the device pins as possible. Remove the

ground plane from the board underneath the

device to eliminate parasitic capacitance. Refer

Printed Circuit Board Layout section for

more layout suggestions.

Pins 6 and 7

Output Voltage (-Vo and +Vo): These are the

differential signal output pins. The output voltage

at these pins is limited to 0.7V to 3.9V. The

output recovery time after exceeding these limits

is approximately 40ns. The output voltage can

be defined as:

Pin 8

Common-Mode Voltage (Vcm): This input sets

the common-mode output operating points. The

common mode input voltage can range from 1.5V

to 3.5V. Refer to

Output Voltage pin discussion

for limitations on the output range.

Load: The CLC503 is intended to drive high speed

CMOS analog-to-digital converters, such as the

CLC949.

Resistive loading will affect the gain and

common mode offset. It is not recommended to drive

resistive loads below 10k

Ω with this part. See Figure 5

for gain vs. load with specified range in device output

resistance.

Figure 5: Gain vs. Resistive Load

Settling Time: The CLC503 settles to 0.1% in 15ns

with a 5pF load, the input capacitance of the CLC949.

Refer to the

Settling Time vs. Capacitive Load plot in

the

Typical Performance Characteristics section.

Power Dissipation

To calculate the power dissipation, PT, for the CLC503,

use the following equation:

The performance of the CLC503 is strongly dependent

on proper layout, and adequate power supply

decoupling. The parasitic capacitance at the output of

the CLC503 and the input to the CLC949, or any other

analog-to-digital converter, must be kept to a minimum.

Consider the following guidelines:

Use a ground plane.

Bypass power supply pins with monolithic

capacitors of 0.1

µF and with 6.8µF tantalum

capacitors. Place the capacitors less than 0.1"

(3mm) from the pin.

Remove the ground plane underneath the

device and 0.1" (3mm) from all input/output

pads.

Interfacing the CLC503 with the CLC949

The CLC503 can be easily interfaced with the CLC949

as shown in Figure 6. An evaluation board is available

for proto-typing and measurements.

=−

()

-V

V+V

-V

ocm

odiff

ocm

=−

−

()

Load Resistance (

Ω)

03 Fi

1.5

100

1000

10000

0.5

100000

2.5

Ro = 600Ω = Romax

Ro = 400Ω = Romin

Design Information

Printed Circuit Board Layout

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