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CLC503 bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện CLC503
Giải thích chi tiết về linh kiện  Comlinear CLC503 180MHz, Differential-Output Amplifier
PDF  6 Pages
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CLC503 bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI)

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CLC503 APPLICATIONS
APPLICATION CONSIDERATIONS
Theory of Operation
Figure 1 is a simplified schematic of the CLC503.
Figure 1: Simplified Block Diagram
The input voltage drives a unity gain buffer, B1, and
an inverting buffer, B2. These buffers drive emitter
followers, Q1 and Q2. Resistor, R3, is the gain set
resistor. The combination of B1, B2, Q1, Q2 and R3
form a transconductance stage.
The input voltage
across R3 is converted to an in-phase and out-of-
phase current through the collectors of Q1 and Q2. The
current through R3 is:
The common mode voltage across R4 is converted
to a current. Transistor Q5 has a collector current
equal to:
The common mode current is scaled and mirrored back
to Q1 and Q2. These currents, I, are converted back to
a voltage at the collector load resistors, R1 and R2.
This forms the common-mode output voltage.
Vocm = VCC – Vdiode – R1I
I = 16Icm
Vocm = Vcm
Figure 2 depicts the differential output voltage limits of
the CLC503.
Figure 2: Differential Output Voltage
Centered around Vcm, the outputs are derived from the
following equations.
The input to output relationship is shown in Figure 3.
Vin
Vodiff
±1V
±2V
2Vpp
4Vpp
±1.4V max
±2.8V max
Figure 3: Input vs. Output Relationship
Pulling the power down line (PDN) high decreases the
quiescent supply current. This
turns off the current
flowing in Q5, and therefore Q1 and Q2, allowing the
output voltages to drift high, to approximately 4.3V.
Since the signal is not significantly attenuated, PDN
does not effectively isolate the input from the output.
This part is not recommended for use as a multiplexer.
Refer to
Pin Descriptions - Power Down pin -
section. No damage occurs to the device when PDN is
high and the input is driven to the supply voltage.
Pin Descriptions
Figure 4: CLC503 Functional Pin Descriptions
4
+1
-Vo
+Vin
B1
Q1
R1
VCC
R3
I
-1
+Vo
B2
Q2
R2
I
R4
Icm
Q5
Q4
Q4
VEE
PDN
Vcm
I3
Current Mirror
R1 = R2
2 R1 = R3
R4 = 16R1
Input Voltage (V)
3.7
0.8
-1
0
1
2.25
3.25V
1.25V
Vcm
+Vo = Vcm +Vin
-Vo = Vcm -Vin
+Vo
Vin
PDN
2
3
1
7
VCC
5
-Vo
6
Vcm
8
VEE
4
I
2V
R
VI R
I R
R
R
VI 2R
V
2V
R
2R
2R
R
V2V
3
in
3
odiff
31
3 2
1
2
odiff
31
odiff
in
3
11
3
odiff
in
=
=+
=
=
()
=
()
=
=
I
VV
V
R
R
16R
cm
CC
cm
diode
4
41
≈
−−
=
+V
V
V
-V
V
V
V+V
-V
2V
ocm
in
ocm
in
odiff
oo
in
=+
=−
==
–(
)
IV
V
V
R
CC
cm
diode
1
=−
−



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