MSM7502 datasheet(12/35 Pages) OKI

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¡ Semiconductor

MSM7502

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CEN

Chip Enable signal input.

When CEN is in digital "0" state, WRN and RDN are valid.

RESETN

Reset signal input.

Digital "0" input to RESETN makes all of internal control registers to be initialized. When

powered on, this RESETN signal should be input for initializing the system.

TIMEN

Watchdog timer output.

When the processor does not reset the timer, the 500 ms period (Digital "0" : 4 ms) digital signal

is continuously output. When RESETN is at digital "0", this timer is reset. And, in about 500 ms

after RESETN goes to digital "1", the first timer output signal is issued and then the timer signal

is output at intervals of a 500 ms. If the SYNC signal is not input, the TIMEN signal is not output.

LML

Control signal output for external hold tone generator.

LML goes to digital "1" state when the hold tone transmit mode on transmit path or the hold

acknowledge tone mode on receive path is selected. During initialized state, LML is in digital "0"

state.

VLCD

By processor control, VLCD outputs a DC voltage between 0 and 1.7 V is about 0.25 V step.

This is used to control the deflection angle of the LCD display. VLCD has the internal resistance

value of about 1 kW, so the external load of over 100 kW should be used. During initialized state,

VLCD outputs the voltage of 0 V.

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