MSM7502 datasheet(9/35 Pages) OKI

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¡ Semiconductor

MSM7502

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BCLOCK

CODEC PCM data I/O shift clock input.

The frequency is one of 64 kHz, 128 kHz, 256 kHz, 512 kHz, 1024 kHz, 2048 kHz, 96 kHz, 192 kHz,

384 kHz, 786 kHz, 1536 kHz, and 1544 kHz. If the BCLOCK signal is not applied, PLL is out of

synchronization and the CODEC path goes into the power down mode.

XSYNC, RSYNC

Synchronous signal input.

CODEC PCM data is sent out sequencially via the PCMOUT pin from MSB at the rising edge of

the BCLOCK signal in synchronization with the rise of the XSYNC signal. PCM data should be

entered via the PCMIN pin with MSB at the head in synchronization with the rise of the RSYNC

signal. PCM data is shifted in at the falling edge of the BCLOCK signal.

Since the XSYNC signal is used for a trigger signal for PLL and for a clock signal to the tone

generator, if this signal is not applied, not only any tone can not be output, but also PLL goes out

of synchronization and the CODEC path goes into a power down mode. This signal has to be

synchronous with the BCLOCK signal and its frequency must be within 8 kHz

±50 ppm to ensure

the CODEC AC characteristics (mainly frequency characteristics).

PCMIN

PCM signal input.

PCMIN data is shifted in at the falling edge of the BCLOCK signal and is latched into the internal

PCMOUT

PCM signal output.

PCMOUT data is shifted out at the rising edge of the BCLOCK signal. PCMOUT is left open after

eight bits are shifted or when PLL goes out of synchronization. PCMOUT also is left open

through processor control. In addition, a digital path between PCMIN and PCMOUT is formed

through processor control. PCMOUT needs a pull-up resistor because of its open-drain circuit.

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