TPS1663 datasheet(30/42 Pages) TI1

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TPS1663

SLVSET9C – SEPTEMBER 2018 – REVISED MARCH 2019

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12 Layout

12.1 Layout Guidelines

•

For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN

terminal and GND.

•

High current carrying power path connections must be as short as possible and must be sized to carry at

least twice the full-load current. See Figure 39 and Figure 40 for a typical PCB layout example.

•

Locate all the TPS1663x family support components R(ILIM), R(PLIM), C(dVdT), R(IMON), UVLO, OVP resistors

close to their connection pin. Connect the other end of the component to the GND with shortest trace length.

•

The trace routing for the R(ILIM), R(PLIM) component to the device must be as short as possible to reduce

parasitic effects on the current limit and power limit accuracy. These traces must not have any coupling to

switching signals on the board.

•

Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the

device they are intended to protect, and routed with short traces to reduce inductance. For example, a

protection Schottky diode is recommended to address negative transients due to switching of inductive loads,

and it must be physically close to the OUT and GND pins.

•

Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater

cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board GND plane

directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase

heat sinking in higher current applications.

TPS1663 bảng dữ liệu(PDF) 30 Page - Texas Instruments