công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

TMP117AIDRVT bảng dữ liệu(PDF) 7 Page - Texas Instruments

Click here to check the latest version.
tên linh kiện TMP117AIDRVT
Giải thích chi tiết về linh kiện  high-accuracy, low-power, digital temperature sensor with SMBus- and I2C-compatible interface
PDF  51 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
Logo TI1 - Texas Instruments

TMP117AIDRVT bảng dữ liệu(HTML) 7 Page - Texas Instruments

Back Button TMP117AIDRVT Datasheet HTML 3Page - Texas Instruments TMP117AIDRVT Datasheet HTML 4Page - Texas Instruments TMP117AIDRVT Datasheet HTML 5Page - Texas Instruments TMP117AIDRVT Datasheet HTML 6Page - Texas Instruments TMP117AIDRVT Datasheet HTML 7Page - Texas Instruments TMP117AIDRVT Datasheet HTML 8Page - Texas Instruments TMP117AIDRVT Datasheet HTML 9Page - Texas Instruments TMP117AIDRVT Datasheet HTML 10Page - Texas Instruments TMP117AIDRVT Datasheet HTML 11Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 51 page
background image
VIH
VIL
SCL
P
S
VIH
VIL
SDA
tBUF
tHD;STA
tLOW
tR
tHD;DAT
tHIGH
tF
tSU;DAT
tSU;STA
tSU;STO
P
S
tVD;DAT
7
TMP117
www.ti.com
SNOSD82B – JUNE 2018 – REVISED MARCH 2019
Product Folder Links: TMP117
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
(1)
The maximum tHD;DAT could be 0.9 µs for Fast-Mode, and is less than the maximum tVD;DAT by a transition time.
(2)
tVD;DATA = time for data signal from SCL "LOW" to SDA output ("HIGH" to "LOW", depending on which is worse).
6.7 Two-Wire Interface Timing
Over free-air tempearture range and V+ = 1.8 V to 5.5 V (unless otherwise noted)
FAST-MODE
UNIT
MIN
MAX
fSCL
SCL operating frequency
1
400
KHz
tBUF
Bus free time between STOP and START conditions
1300
ns
tHD;STA
Hold time after repeated START condition.
After this period, the first clock is generated(1)
600
ns
tSU;STA
Repeated START condition setup time
600
ns
tSU;STO
STOP condition setup time
600
ns
tHD;DAT
Data hold time
0
ns
tVD;DAT
Data valid time(2)
0.9
µs
tSU;DAT
Data setup time
100
ns
tLOW
SCL clock low period
1300
ns
tHIGH
SCL clock high period
600
ns
tF – SDA
Data fall time
20 ×
(V+ /5.5)
300
ns
tF, tR – SCL
Clock fall and rise time
300
ns
tR
Rise time for SCL
≤ 100 kHz
1000
ns
Serial bus timeout (SDA bus released if there is no clock)
20
40
ms
Figure 1. Two-Wire Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com