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ES7243 bảng dữ liệu(PDF) 8 Page - Suzhou Everest Semiconductor Co. Ltd.

tên linh kiện ES7243
Giải thích chi tiết về linh kiện  High Performance Stereo Audio ADC
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nhà sản xuất  EVEREST [Suzhou Everest Semiconductor Co. Ltd.]
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ES7243 bảng dữ liệu(HTML) 8 Page - Suzhou Everest Semiconductor Co. Ltd.

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Everest Semiconductor
Confidential
ES7243
Revision 10.0
8
March 2019
Latest datasheet: www.everest-semi.com or info@everest-semi.com
Digital Voltage Level
Input High-level Voltage
0.7*VDDP
V
Input Low-level Voltage
0.5
V
Output High-level Voltage
VDDP
V
Output Low-level Voltage
0
V
SERIAL AUDIO PORT SWITCHING SPECIFICATIONS
PARAMETER
Symbol
MIN
MAX
UNIT
MCLK frequency
49.2
MHz
MCLK duty cycle
40
60
%
LRCK frequency
200
KHz
LRCK duty cycle (Note 2)
40
60
%
SCLK frequency
26
MHz
SCLK pulse width low
TSLKL
16
ns
SCLK Pulse width high
TSCLKH
16
ns
SCLK falling to LRCK edge (master mode only)
TSLR
10
ns
LRCK edge to SCLK rising (slave mode only)
TLSR
10
ns
SCLK falling to SDOUT valid
VDDD=3.3V TSDO
16
ns
LRCK edge to SDOUT valid (Note 3)
VDDD=3.3V TLDO
11
ns
Note 2: one SCLK period of high time in DSP/PCM modes.
Note 3: only apply to MSB of Left Justified or DSP/PCM mode B.
Figure 6 Serial Audio Port Timing
I2C SWITCHING SPECIFICATIONS
PARAMETER
Symbol
MIN
MAX
UNIT
SCL Clock Frequency
FSCL
400
KHz
Bus Free Time Between Transmissions
TTWID
1.3
us
Start Condition Hold Time
TTWSTH
0.6
us
Clock Low time
TTWCL
1.3
us
Clock High Time
TTWCH
0.4
us
Setup Time for Repeated Start Condition
TTWSTS
0.6
us
SDA Hold Time from SCL Falling
TTWDH
900
ns
SDA Setup time to SCL Rising
TTWDS
100
ns
Rise Time of SCL
TTWR
300
ns
Fall Time SCL
TTWF
300
ns
TSCLKH
TLDO
TSDO
TLSR
TSLR
TSCLKL
SDOUT
SCLK
LRCK



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