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AXP288
PMIC Optimized For Multi-Core High-Performance System
AXP288 Datasheet V1.06
Copyright © 2014 X-Powers Limited. All Rights Reserved.
37
BYT and CHT SoC Initiated Cold Reset
T0
Cold Off
Sequence
Cold boot
Sequence
Re-boot if CLDRSTEN=1
Figure 9-11
Table 9-10
Cold Reset scenario 2:
The diagram below shows the second special case of a cold reset being enabled based on a global reset and the PMIC register
bit being set.
T0
Continue Cold Off
Sequence ignoring
SUSPWRDNACK signal
Global Reset sequence turned into Cold Reset Sequence
PLTRST_B
SLP_S0IX_B
Signals from SoC
COLDRESETEN1 = 1
Cold boot
Sequence
starts
Figure 9-12
Table 9-11
Parameter
Description
Min
Typical
Max
Units
T0
Time delay between power down
complete and power up start
50
ms
Parameter
Description
Min
Typical
Max
Units
T0
Time delay between power down
complete and power up start
50
ms



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