STC89LE53RC datasheet(84/165 Pages) STC

84 / 165 page

6.4 How Interrupts Are Handled

Each interrupt flag is sampled at every system clock cycle. The samples are polled during the next system clock.

If one of the flags was in a set condition at first cycle, the second cycle(polling cycle) will find it and the interrupt

system will generate an hardware LCALL to the appropriate service routine as long as it is not blocked by any of

the following conditions.

Block conditions :

An interrupt of equal or higher priority level is already in progress.

The current cycle(polling cycle) is not the final cycle in the execution of the instruction in progress.

The instruction in progress is RETI or any write to the IE or IP registers.

The ISP/IAP activity is in progress.

Any of these four conditions will block the generation of the hardware LCALL to the interrupt service routine.

Condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine.

Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one or more

instruction will be executed before any interrupt is vectored to.

The polling cycle is repeated with the last clock cycle of each instruction cycle. Note that if an interrupt flag is

active but not being responded to for one of the above conditions, if the flag is not still active when the blocking

condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag

was once active but not being responded to for one of the above conditions, if the flag is not still active when the

blocking condition is removed, the denied interrupt will not be serviced. The interrupt flag was once active but

not serviced is not kept in memory. Every polling cycle is new.

•

6.3 Interrupt Priorities

Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a

bit in Special Function Registers IP or XICON and IPH . A low-priority interrupt can itself be interrupted by a

high-pority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by

any other interrupt source.

If two requests of different priority levels are received simultaneously, the request of higher priority level

is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence

determines which request is serviced. Thus within each priority level there is a second priority structure

determined by the polling sequence,as follows:

Source

Priority Within Level

IE0

0(highest)

TF0

IE1

TF1

RI +Tl

TF2+EXF2

IE2

IE3

Note that the “priority within level” structure is only used to resolve simultaneous requests of the same prionty

level.

STC89LE53RC bảng dữ liệu(PDF) 84 Page - STCmicro Technology Co,.Ltd

STC89LE53RC bảng dữ liệu(HTML) 84 Page - STCmicro Technology Co,.Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL