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STC89LE53RC bảng dữ liệu(PDF) 78 Page - STCmicro Technology Co,.Ltd

tên linh kiện STC89LE53RC
Giải thích chi tiết về linh kiện  Enhanced 80C51 Central Processing Unit ,6T or 12T per machine cycle
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There are 8 interrupt vector addresses available in STC89xx series. Associating with each interrupt vector, each
interrupt source can be individually enabled or disabled by setting or clearing a bit in the registers IE and XICON.
The register also contains a global disable bit(EA), which can be cleared to disable all interrupts at once.
Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPH and
the other in IP or XICON register. Higher-priority interrupt will be not interrupted by lower-priority interrupt
request. If two interrupt requests of different priority levels are received simultaneously, the request of higher
priority is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling
sequence determine which request is serviced. The following table shows the internal polling sequence in the
same priority level and the interrupt vector address.
Chapter 6 Interrupt
Interrupt Source
Vector
address
Polling
Sequence
Interrupt
Priority setting
(IP/XICON,IPH)
Priority 0
(lowest)
Priority
1
Priority
2
Priority 3
(highest)
Interrupt
Request
Interrupt
Enable
Control Bit
/INT0
(External interrupt 0)
0003H 0(highest)
PX0H,PX0
0,0
0,1
1,0
1,1
IE0
EX0/EA
Timer 0
000BH
1
PT0H,PT0
0,0
0,1
1,0
1,1
TF0
ET0/EA
/INT1
(External interrupt 1)
0013H
2
PX1H,PX1
0,0
0,1
1,0
1,1
IE1
EX1/EA
Timer1
001BH
3
PT1H,PT1
0,0
0,1
1,0
1,1
TF1
ET1/EA
UART
(Serial Interface)
0023H
4
PSH,PS
0,0
0,1
1,0
1,1
RI+TI
ES/EA
Timer 2
002BH
5
PT2H,PT2
0,0
0,1
1,0
1,1
TF2+EXF2
ET2/EA
/INT2
0033H
6
PX2H,PX2
0,0
0,1
1,0
1,1
IE2
EX2/EA
/INT3
003BH 7(lowest)
PX3H,PX3
0,0
0,1
1,0
1,1
IE3
EX3/EA
78



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